VLSI Circuits for MIMO Communication Systems
ReferencePh.D. dissertation, ETH Zurich, Switzerland, 2006.
AbstractMultiple-input multiple-output (MIMO) systems are widely recognized as the enabling technology for future wireless communication systems. In particular the use of spatial multiplexing allows to achieve a linear increase in capacity with the minimum of the number of antennas employed at the transmitter and at the receiver. Unfortunately, these capacity gains are bought dearly at the expense of higher silicon complexity at the receiver. In particular, the separation of the spatially multiplexed streams poses a considerable research challenge.
So far, most publications in this field have focused on complexity reduction of algorithms with software programmable architectures in mind. However, such implementations can not meet the requirements of wideband MIMO systems and the corresponding optimizations are often not immediately applicable or are not even advantageous for dedicated VLSI circuits. Unfortunately, even the very few reported VLSI implementations of MIMO detection are not able to meet the requirements (in terms of throughput or latency) of envisioned future MIMO communication systems.
Hence, in this thesis we focus on the VLSI implementation of MIMO detection algorithms for spatial multiplexing. In particular, linear and successive interference cancellation, exhaustive search maximum likelihood, and sphere and K-best decoding are considered. To this end, corresponding optimized algorithms and techniques for complexity reduction are developed which are specifically tailored to the requirements of VLSI circuits. Based on these considerations, novel low-complexity VLSI architectures are proposed. Finally, our implementations provide reference for the true silicon complexity of this kind of algorithms.
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